Method and system for improving yield of an integrated circuit
US7493574B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2006 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Oct 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system for improving yield of an integrated circuit are disclosed. The method includes optimizing a design of the integrated circuit according to a set of predefined design parameters to generating design points that meet a set of predefined design specifications, analyzing the design points to form clusters comprising the design points, determining a representative design point from the clusters comprising the design points, running a statistical simulation to determine a yield of the design using the representative design point and a statistical model of manufacturing process variations, generating statistical corners in accordance with results of the statistical simulation, and optimizing the design in accordance with the statistical corners using an iterative process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.