Method of manufacturing a chip
US7494909B2 · kind B2 · utility
4Cited by
6References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Dec 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.