Apparatus and method for test, characterization, and calibration of microprocessor-based and digital signal processor-based integrated circuit digital delay lines
US7495429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2005 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Nov 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00097
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit board with a processing unit and a delay line with a controllable number of delay elements fabricated thereon includes apparatus for testing and calibrating the delay line elements. In the test mode, a calibrated pulse is delayed by the delay line while determining the logic state of pulse at two times, the interval between the two times being the same as the pulse width. By adding delay elements, the period of the calibrated pulse as a function of number of delay elements can determine the delay of each delay element. In the calibration mode, the delay line is configured as a ring oscillator and the frequency of the ring oscillator as a function of number of delay elements provides the time delay for the individual elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.