Electrostatic discharge protection in a semiconductor device
US7495873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2004 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Jan 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
An ESD protection circuit for protecting a circuit from an ESD event occurring between a first voltage supply node and a second voltage supply node associated with the circuit to be protected includes an MOS device having a gate terminal, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal is connected to the first voltage supply node and the second source/drain terminal is connected to the second voltage supply node. The ESD protection circuit further includes a trigger circuit coupled to the gate terminal of the MOS device. The trigger circuit is configured to generate a control signal at the gate terminal of the MOS device for activating the MOS device during the ESD event. At least a portion of the trigger circuit is formed in a floating well which becomes biased to a voltage that is substantially equal to a first voltage when the first voltage is supplied to the first voltage supply node or to a second voltage when the second voltage is applied to the second voltage supply node, whichever voltage is greater.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.