Packet processing device implementing scheduling and priority for improved efficiency
US7496034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2005 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Sep 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet transmission device improved in packet transmission efficiency. Each packet input processor generates a pointer and identifies a packet type with respect to a received packet, and generates identification data including the pointer and the packet type identification result. A memory access controller detects a header readout amount of the packet based on the packet type identification result, generates first readout data including the header readout amount and a readout pointer indicative of a storage location of the packet in a shared memory, and adaptively reads out header data of the packet from the shared memory in accordance with the first readout data. A protocol processor analyzes the destination of the read header data, and a packet updater updates the old destination address of the packet to a new one to generate a packet with the updated destination address, and outputs the generated packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.