Techniques for jitter buffer delay management
US7496086B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Jan 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/6494
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Techniques are provided to allow a jitter buffer to automatically reach a quiescent number of packets in the jitter buffer, based on current network conditions. Generally, no explicit jitter buffer delay is assumed, and a current packet is repeat played if no new packets are available in the jitter buffer. If there are too many packets in the jitter buffer, a newly received packet is discarded. When a packet is replayed, the delay associated with a jitter buffer is effectively increased. This is not an explicit jitter buffer delay, but, instead, there is an implicit delay associated with the jitter buffer. When a packet is discarded, the delay associated with a jitter buffer is effectively decreased. Again, this is an implicit jitter buffer delay. By repeat playing packets and discarding packets when the jitter buffer is full, an appropriate level of packets may be determined and maintained in the jitter buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.