Storage efficient sliding window sum
US7496167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Aug 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A delay buffer includes a first shift register receiving input data and having a shift signal input port. The first shift register right shifts the input data responsive to a shift signal on the shift signal input port. The shift signal is determined based on an effective bit width of the input data. A first delay line receives the shifted data from the first shift register while a second delay line of equal length to the first delay line receives the shift signal. A second shift register receives the output from the first delay line and receives the output of the second delay line on a shift signal input port. The second shift register then left shifts the data contained therein according to the shift signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.