System and method for a fast fourier transform architecture in a multicarrier transceiver
US7496618B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2004 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Nov 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/265
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A Fourier transform architecture and system for FFT and IFFT processing within multicarrier transceiver is disclosed that includes a programmable butterfly component, a memory and a programmable address generation unit. The architecture includes a butterfly component configured to perform a plurality of radix butterfly calculations, and a four bank memory configured to operate on sample data. The architecture further includes a programmable address generation unit coupled to the pipeline to enable the architecture to perform calculations independent of Fourier-based algorithms. A method for addressing memory banks for an FFT pipeline includes expressing an index in radix notation, computing a bank address for a bank memory, converting the bank address to a reduced size by ignoring one or more bits, and calculating the bank address within the reduced memory bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.