DMA descriptor queue read and cache write pointer arrangement
US7496699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2005 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Nov 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for retrieving buffer descriptors from a host memory for use by a peripheral device. In an embodiment, a peripheral device such as a NIC includes a plurality of buffer descriptor caches each corresponding to a respective one of a plurality of host memory descriptor queues, and a plurality of queue descriptors each corresponding to a respective one of the host memory descriptor queues. Each of the queue descriptors includes a host memory read address pointer for the corresponding descriptor queue, and this same read pointer is used to derive algorithmically the descriptor cache write addresses at which to write buffer descriptors retrieved from the corresponding host memory descriptor queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.