Proximity communication-based off-chip cache memory architectures
US7496712B1 · kind B1 · utility
6Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2005 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Mar 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A proximity interconnect module includes a plurality of off-chip cache memories. Either disposed external to the proximity interconnect module or on the proximity interconnect module are a plurality of processors that are dependent on the plurality of off-chip cache memories for servicing requests for data. The plurality of off-chip cache memories are operatively connected to either one another or to one or more of the plurality of processors by proximity communication. Each of the plurality of off-chip cache memories may cache certain portions of the physical address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.