ROM addressing method for an ADPCM decoder implementation
US7496720B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 2007 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Mar 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B14/04
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address(es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.