Systems and methods for maintaining lock step operation
US7496786B2 · kind B2 · utility
19Cited by
1References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Apr 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is provided for rapidly synchronizing two or more processing elements in a fault-tolerant computing system. Embodiments of this system allow for the rapid synchronization of two processing elements through partial copies of the contents of memory associate with each processing element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.