Electrostatic discharge failure avoidance through interaction between floorplanning and power routing
US7496877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2005 |
| Grant date | Feb 24, 2009 |
| Priority date | — |
| Expiry date | Apr 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.