ESD protection circuit for semiconductor device
US7498638B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 10, 2007 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Jul 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An ESD protection circuit for a semiconductor device including a bonding pad receiving a first power supply voltage; an interconnect layer provided in an underside of the bonding pad so as to be electrically conductive with the bonding pad; a semiconductor substrate provided with a first well of a predetermined conductive type in a predetermined region of a surface layer of the substrate, which first well receives a second power supply voltage having a different voltage from the first power supply voltage and provided with a confronting region confronting the underside of the interconnect layer over a dielectric layer, and the first well of the semiconductor substrate, the dielectric layer, the bonding pad and the interconnect layer constitute a capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.