Buffer circuit having multiplexed voltage level translation
US7498860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2007 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Mar 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01759
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.