Programmable compute system for executing an H.264 binary decode symbol instruction
US7498960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2007 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Apr 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/4006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A compute system for executing an h.264 binary decode symbol instruction including a first compute unit having a range normalization circuit and an rLPS update circuit, and operating in a first mode responsive to current rLPS, range, value and current context to generate the next normalized range and next rLPS for the current context; a second compute unit including a value update circuit, a context update circuit, and value normalization circuit responsive to current rLPS, range value and current context to obtain the output bit, normalized value and the updated current context; and a third compute unit or said first compute unit operating in a second mode including a range circuit and a next context rLPS circuit responsive to rLPS range, value and next context to obtain a next context rLPS value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.