Low loss SOI/CMOS compatible silicon waveguide
US7499620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2006 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Mar 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/025
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method and structure for reducing optical signal loss in a silicon waveguide formed within a silicon-on-insulator (SOI) structure uses CMOS processing techniques to round the edges/corners of the silicon material along the extent of the waveguiding region. One exemplary set of processes utilizes an additional, sacrificial silicon layer that is subsequently etched to form silicon sidewall fillets along the optical waveguide, the fillets thus “rounding” the edges of the waveguide. Alternatively, the sacrificial silicon layer can be oxidized to consume a portion of the underlying silicon waveguide layer, also rounding the edges. Instead of using a sacrificial silicon layer, an oxidation-resistant layer may be patterned over a blanket silicon layer, the pattern defined to protect the optical waveguiding region. A thermal oxidation process is then used to convert the exposed portion of the silicon layer into silicon dioxide, forming a bird's beak structure at the edges of the silicon layer, thus defining the “rounded” edges of the silicon waveguiding structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.