Method and apparatus for managing a cache memory in a mass-storage system
US7500063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2005 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Aug 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0866
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments of the present invention relate to a method and a circuit for managing the prefetching of data into a cache. According to some embodiments of the present invention a prefects controller may be adapted to trigger a prefetch operation for prefetching one or more data segments into the cache together with at least one segment to be fetched, and may be further adapted to establish a number of data segments to be prefetched together with the at least one segment to be fetched. According to some embodiments of the present invention, the prefetch controller may be adapted to establish what number of segments are to be prefetched at least in accordance with the number of successive segments, including one, already in the cache, which are spaced apart by no more than a predetermined number of segments relative to the at least one segment to be fetched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.