Method and apparatus for sharing instruction memory among a plurality of processors
US7500066B2 · kind B2 · utility
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3References
23Claims
0Family size
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Key dates
| Filing date | Apr 30, 2005 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Jan 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessing apparatus includes a memory and a plurality (M) of processors coupled to share the memory. Access to the memory is time-division multiplexed among the plurality of processors. In one embodiment, a selected processor retrieves M words of instruction forming K instructions during a given clock cycle. The selected processor executes M−K NOP instructions if K<M.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.