Power-up implementation for block-alterable memory with zero-second erase time
US7500081B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Jun 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A block-alterable memory, e.g., a flash memory, having substantially zero erase time is coupled to host. The block-alterable memory includes a controller that reads block information from the memory on power up to determine if a block of the memory is usable. The controller updates block map latches only if the block is usable. The controller also updates block status latches according to the block information. Thus, information about each block of the memory is easily accessible in the latches when the block alterable memory becomes ready for use on power up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.