Apparatus and method for reducing power consumption in a graphics processing device
US7500123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Feb 28, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Briefly, the present invention includes a method and an apparatus for reducing power consumption in a graphics processing device. The apparatus and method include a memory module monitoring device operative to receive a memory module status signal from memory modules. The memory module monitoring device is operative to generate a clock control signal in response to the memory module status signal. The apparatus and method further include a clock cycle reduction circuit coupled to the monitoring module. The clock cycle reduction circuit receives the clock control signal. The clock cycle reduction circuit generates a reduced cycle clock signal in response to the clock control signal such that the reduced cycle clock signal reduces power consumption in the graphics processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.