Patent · US Active

Test system and method

US7500147B2 · kind B2 · utility

1Cited by

6References

18Claims

0Family size

Assignee

VIA Technologies, Inc. · TW

Inventors

Jason Lai · Taipei, TW
Yen-Liang Chen · Hsinchu, TW

Key dates

Filing date	Nov 1, 2005
Grant date	Mar 3, 2009
Priority date	—
Expiry date	Apr 24, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/263
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A test system includes a terminal host and a to-be-tested circuit board. The terminal host generates a trigger signal. The to-be-tested circuit board includes a system chip, a memory and a processor. The system chip receives the trigger signal from the terminal host and generates an interrupt. The memory stores a test program code corresponding to the interrupt. The processor receives the interrupt and executes the test program code corresponding to the interrupt stored in the memory to generate a test result. The system chip transmits the test result to the terminal host.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.