System and method for automatically generating a hierarchical register consolidation structure
US7500228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2004 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Feb 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for, and method of, automatically generating a hierarchical register consolidation structure. In one embodiment, the system includes: (1) a graph generator that parses a High-level Design Language (HDL) file to generate an intermediate graph containing definitions of microprocessor-accessible registers, node interrelationships and summary bits and masks associated with alarm registers, (2) a graph converter, associated with the graph generator, that selectively adds virtual elements and nodes to the intermediate graph to transform the intermediate graph into a mathematical tree and (3) a description generator, associated with the graph converter, that employs the mathematical tree to generate a static tree description in a programming language suitable for use by a device-independent condition management structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.