Parallel filter check using an arithmetic memory location
US7500233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2005 |
| Grant date | Mar 3, 2009 |
| Priority date | — |
| Expiry date | Apr 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Performing parallel comparisons of variables to determine program code execution flow or to compare multiple variables is disclosed. Memory locations are packed with multiple sub-variables for comparison to sub-variables generated, for example, at runtime. Each binary sub-variable includes a “carryout” bit used to determine whether a comparison of one sub-variable with another sub-variable results in a “true” or a “false.” A modified version of twos complement arithmetic is performed on a set of sub-variables. The modified version involves inverting each bit of the sub-variables, performing a masking operation to change the carryout bits to 0, adding a binary 1 to each sub-variable, and performing the masking operation a second time to change the carryout bits to 0. The result of the modified twos complement arithmetic is added to a variable, and the carryout bit of each sub-variable of the resulting variable is evaluated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.