Method for forming a semiconductor structure having nanometer line-width
US7501348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2007 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Apr 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the Γ-shaped metal gate with nano scale line-width can be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.