Cascode circuit employing a depletion-mode, GaN-based FET
US7501670B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2007 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Apr 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/84
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.