Semiconductor chip-embedded substrate and method of manufacturing same
US7501696B2 · kind B2 · utility
21Cited by
27References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2005 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Nov 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/185
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip-embedded substrate comprising a supporting substrate and an insulating layer thereon, members for the connection to external circuits, and a plurality of semiconductor chips embedded in the insulating layer, wherein at least some of the plurality of semiconductor chips are embedded as a stack or stacks thereof. A method of manufacturing such a semiconductor chip-embedded substrate is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.