Semiconductor integrated circuit and method of manufacturing the same
US7501710B2 · kind B2 · utility
2Cited by
6References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 18, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Nov 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/998
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit (1) having an integrated circuit region (1a), and a plurality of I/O cells (6) each having an element formation region for external electrical connection from the element formation region. An input/output signal electrode pad (3), a power supply electrode pad (4) and a GND electrode pad (5) are placed on an element formation region of each I/O cell (6).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.