Comparator with low offset voltage
US7501862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2007 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Sep 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356121
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential comparator is provided. The comparator receiving two differential signals and generating a comparison result represented by an output signal on one of two output terminals respectively on two current paths. The comparator comprises two pairs of latch transistors respectively disposed on the two current paths and two pairs of input transistors respectively disposed on the two current paths, wherein gates of the latch transistors on one of the current paths are commonly coupled to the output terminal between the latch transistors on the other current path, gates of the input transistors on one of the current paths respectively receives an input signal of one of the differential signals and a reference signal of the other differential signal and each of the input transistors is disposed between the output terminal and one of the latch transistors on the current path thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.