High frequency differential voltage level shifter
US7501875B1 · kind B1 · utility
1Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Sep 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35613
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A design for a high speed differential voltage level shifter circuit arrangement utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.