Phase-locked loop bandwidth calibration
US7501900B2 · kind B2 · utility
4Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Feb 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel circuit for obtaining the bandwidth of a phase-locked loop circuit is disclosed. The circuit adjusts a phase of a signal (reference or generated), causing the phase-locked loop circuit to adjust the frequency of its voltage-controlled oscillator as it recovers a phase lock. The circuit times the duration of the recovery stage, from which the loop bandwidth may be obtained. Adjustments to the programmable portions of the phase-locked loop may then be made in accordance with design specifications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.