Video processing subsystem architecture
US7502075B1 · kind B1 · utility
2Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2005 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Apr 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/0084
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video processing apparatus includes a plurality of processing modules, each performing an image processing function, and a central memory interface. The central memory interface accepts read and write memory the said plurality of processing modules and issues burst memory access requests to an external memory by gathering plural memory access requests from the processing modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.