Multilayer chip capacitor
US7502216B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2008 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Jan 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G4/30
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multilayer chip capacitor includes: a capacitor body; internal electrodes disposed in the capacitor body, each internal electrode having one or more lead; and external electrodes disposed on first and second side surfaces of the capacitor body to be electrically connected to the internal electrodes through the leads. The average number of leads in each internal electrode is smaller than half (½) of the total number of external electrodes. The leads of the internal electrodes having opposite polarities and adjacent in the lamination direction are disposed to be adjacent to each other as seen from the lamination direction. All the internal electrodes having the same polarity are electrically connected to each other in the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.