Method and circuit for adaptive equalization of multiple signals in response to a control signal generated from one of the equalized signals
US7502411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2004 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Aug 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03019
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal. In other embodiments, the invention is an adaptive equalization circuit including an equalization filter and circuitry for generating a control signal for the filter in response to a signal indicative of a predetermined fixed pattern, a receiver including an adaptive equalization circuit, a system including such a receiver, and a method for adaptive equalization of signals received over a multi-channel serial link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.