Method and apparatus for rescheduling operations in a processor
US7502912B2 · kind B2 · utility
20Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2003 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Mar 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for rescheduling operations in a processor. More particularly, the present invention relates to optimally using a scheduler resource in a processor by analyzing, predicting, and sorting the write order of instructions into the scheduler so that the duration the instructions sit idle in the scheduler is minimized. The analyses, prediction, and sorting may be done between an instruction queue and a scheduler by using delay units. The prediction can be based on history (latency, dependency, and resource) or on a general prediction scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.