Error correction apparatus, systems, and methods
US7502959B2 · kind B2 · utility
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Key dates
| Filing date | Jul 28, 2003 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Nov 18, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2242
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.