Method and apparatus for detecting presence of errors in data transmitted between components in a data storage system using an I2C protocol
US7502992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Mar 10, 2009 |
| Priority date | — |
| Expiry date | Mar 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0094
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data storage system includes a storage processor that is configured to perform load and store operations on a storage array on behalf of external devices. The data storage system also includes a controller that isolates communication between the external devices when coupled to the storage array via the storage processor. The controller further maintains a set of registers that store information associated with the data storage system and allows the storage processor to access the register via an I2C bus. The system utilizes an error detection procedure to allow detection of errors in the data transmitted between the controller and the storage processor. During operation, a checksum value is transmitted between the controller and the storage processor using the I2C bus during a register write or read procedure. The controller and the storage processor utilize the checksum value in an error detection procedure to detect the data errors resulting in transmission of the data by the I2C bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.