Fault tolerant asynchronous circuits
US7504851B2 · kind B2 · utility
37Cited by
12References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2007 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Apr 25, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.