System and method for providing an ultra low power scalable digital-to-analog converter (DAC) architecture
US7504979B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 21, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Sep 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/765
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method are disclosed for providing an ultra low power scalable digital-to-analog converter architecture. Refresh buffer circuits are provided to buffer a voltage reference resistor string. The refresh buffer circuits may be coupled to the resistor string at selected binary fold points. The refresh buffer circuits can reduce the output impedance of the resistor string. Also, each digital-to-analog converter channel can be provided with a multi-dimensional multiplexer that minimizes settling time. The number of refresh buffer circuits and the number of dimensions of the multiplexer can be selected to maximize circuit performance for a given load capacitance and bit rate of the digital-to-analog converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.