Laminated bond of multilayer circuit board having embedded chips
US7505282B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Jul 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/049
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multilayer circuit board has a bottom and an upper multilayer circuit boards, a glue layer, multiple outer contact vias and two insulating lacquer layers. The bottom and the upper multilayer circuit boards respectively have multiple conductive wires, an insulating layer, a frame, multiple chips, a press laminate, a patterned conductive layer and at least one inner contact via. The glue layer sticks the bottom and the upper multilayer circuit boards together. The multiple contact vias are formed through the bottom and the upper multilayer circuit boards to electronically interconnect the conductive wires and the patterned conductive layers in the bottom and the upper multilayer circuit boards. The insulating lacquer layers are respectively coated under and on portions of the patterned conductive layers in the bottom and the upper multilayer circuit boards to protect the patterned conductive layers, wherein the un-coated patterned conductive layers become multiple contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.