Fault tolerant asynchronous circuits
US7505304B2 · kind B2 · utility
33Cited by
7References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2007 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Apr 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.