Method for automatic generation of finite element mesh from IC layout data
US7505884B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | May 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention includes a method for performing a thermal analysis, including the steps of determining size and placement of each of a plurality of drivers on an integrated circuit device. The determined size and placement of each driver is stored as layout data and the layout data is converted into input for a finite element analysis program. The input is applied to the finite element analysis program, and the finite element analysis program is used to construct a finite element mesh of the integrated circuit device from the input. Additionally, material properties are assigned to the finite element mesh, and a thermal analysis is performed of the finite element mesh to generate data in a thermal analysis report.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.