High performance content alteration architecture and techniques
US7505946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2004 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Sep 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06Q30/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a unique system and method that facilitates obtaining high performance and more secure HIPs. More specifically, the HIPs can be generated in part by caching pre-rendered characters and/or pre-rendered arcs as bitmaps in binary form and then selecting any number of the characters and/or arcs randomly to form a HIP sequence. The warp field can be pre-computed and converted to integers in binary form and can include a plurality of sub-regions. The warp field can be cached as well. Any one sub-region can be retrieved from the warp field cache and mapped to the HIP sequence to warp the HIP. Thus, the pre-computed warp field can be used to warp multiple HIP sequences. The warping can occur in binary form and at a high resolution to mitigate reverse engineering. Following, the warped HIP sequence can be down-sampled and texture and/or color can be added as well to improve its appearance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.