System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories
US7506081B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2004 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Mar 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.