Shared memory multiprocessor system
US7506107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Mar 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a shared memory multiprocessor system, data reading accesses and data write-back completion notifications are selected in synchronism with all of the nodes to order them. In each of the nodes, a subject address of ordered data reading access is compared with a subject address of ordered data write-back completion notification to detect a data reading operation of the same address which is passed by the completion of the data writing-back operation. Both a data reading sequence and a data writing-back sequence are determined. At this time, such a coherency response for prompting a re-reading operation of the data is transmitted to the node which transmitted the data reading access, so that coherency of the data is maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.