Complier assisted victim cache bypassing
US7506119B2 · kind B2 · utility
4Cited by
0References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Mar 14, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for compiler assisted victim cache bypassing including: identifying a cache line as a candidate for victim cache bypassing; conveying a bypassing-the-victim-cache information to a hardware; and checking a state of the cache line to determine a modified state of the cache line, wherein the cache line is identified for cache bypassing if the cache line that has no reuse within a loop or loop nest and there is no immediate loop reuse or there is a substantial across loop reuse distance so that it will be replaced from both main and victim cache before being reused.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.