Method and apparatus for register renaming using multiple physical register files and avoiding associative search
US7506139B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2006 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Apr 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at the instruction dispatch or wake-up/issue time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.