Wrapper testing circuits and method thereof for system-on-a-chip
US7506231B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2007 |
| Grant date | Mar 17, 2009 |
| Priority date | — |
| Expiry date | Jun 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a decoding logic and a plurality of wrapper boundary registers. The decoding logic has a signal decoding table which receives and decodes the control signals and then issues decoded signals according to the signal decoding table. The WBR shifts, updates and captures the test signals for the core circuit to execute and output the result signals according to the decoded signals. In comparison with prior art, the testing time is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.