Device package and methods for the fabrication and testing thereof
US7508065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2006 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Oct 31, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/0222
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.