Full-adder of complementary carry logic voltage compensation
US7508233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2007 |
| Grant date | Mar 24, 2009 |
| Priority date | — |
| Expiry date | Jan 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/501
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a full-adder of complementary carry logic voltage compensation, two input terminals of a first multiplexer are connected to a carry input and a carry inverted phase input respectively; an add signal is connected to a select signal; an input terminal of a first inverter is connected to an output signal of the first multiplexer. Two input terminals of a second multiplexer output an addend and a summand; an output signal of the first inverter is selected; an output terminal of the second multiplexer produces a carry signal; an input terminal of the second inverter is connected to an output signal of the second multiplexer for producing a carry inverted phase signal; two input terminals of a third multiplexer input the summand and carry inverted phase signal; an output signal of the first inverter is a select signal; and an output terminal of the third multiplexer produces a sum signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.